EUROPEAN CONGRESS AND EXHIBITION ON ADVANCED MATERIALS AND PROCESSES - EUROMAT 2021

The controlled alignment and assembly of single, bottom-up grown nanowires on a target device substrate is an omnipresent challenge but indispensable for a reproducible fabrication of nanoscale electronic devices. Among various transfer techniques, nanowire contact printing (CP) due to mechanical shearing of the nanowire growth and the prospective device substrate enables immediate parallel nanowire alignment and density control. Nevertheless, CP is frequently associated with an undesirable particle contamination, mechanical substrate wear and with the need to modify appropriately the target substrate, e.g. by so-called nanowire catchers, to enable single-nanowire deposition.

Therefore, we introduce a soft transfer printing (STP) strategy that is combined with CP on a single platform. CP as well as STP were realized with an in-house built three-axis printing tool that enabled lateral velocity control, 200 nm positioning resolution and vertical force adjustment up to 10 N. We transferred silicon nanowires that were synthesized by gold-catalyzed vapor liquid solid growth in a quartz tube reactor at 550 °C with monosilane (SiH4) as a precursor gas. The silicon nanowires were transferred from their growth substrate onto a so-called transfer substrate by CP, which directly yields a parallel nanowire alignment. These aligned nanowires are subsequently adhered to a microscale patterned soft polydimethylsiloxane (PDMS) stamp and subsequently transferred to the target surface, e.g. to silicon substrates. With this technique, patterned assemblies of silicon nanowires were created in a controlled manner. We discuss furthermore, the effect of the utilized printing pressures, the achievable alignment yield, the impact of plasma surface modifications, e.g. by O2 plasma, as well as the influence of the patterning of the PDMS stamp on the ability to yield single-nanowire deposition. Using our nanowire transfer technique, single-nanowires were successfully integrated into a prospective field-effect transistor configuration.